Patent attributes
A semiconductor device includes gate electrodes stacked to be spaced apart from each other on a substrate in a first direction, extending in a second direction, and including pad regions bent in a third direction, sacrificial insulating layers extending from the gate electrodes to be stacked alternately with the interlayer insulating layers, separation regions penetrating through the gate electrodes, extending in the second direction, and spaced apart from each other to be parallel to each other, and a through-wiring region spaced apart from the separation regions to overlap the pad regions between the separation regions adjacent to each other and including contact plugs penetrating through the pad regions. The through-wiring region includes slit regions, and each of the slit regions is disposed to penetrate through the sacrificial insulating layers on one side of a respective pad region.
