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US Patent 11557650 Semiconductor device and manufacturing method thereof
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Patent
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Date Filed
April 23, 2020
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Date of Patent
January 17, 2023
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Patent Application Number
16856817
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Patent Citations
US Patent 10840329 Nanosheet transistor having improved bottom isolation
US Patent 10943830 Self-aligned structure for semiconductor devices
US Patent 10074575 Integrating and isolating nFET and pFET nanosheet transistors on a substrate
US Patent 10134640 Semiconductor device structure with semiconductor wire
US Patent 10164041 Method of forming gate-all-around (GAA) FinFET and GAA FinFET formed thereby
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US Patent 10332803 Hybrid gate-all-around (GAA) field effect transistor (FET) structure and method of forming
US Patent 10464041 Structured packing element having a spiral helix shape
US Patent 10665669 Insulative structure with diffusion break integral with isolation layer and methods to form same
US Patent 10680083 Oxide isolated fin-type field-effect transistors
US Patent 10026829 Semiconductor device with isolated body portion
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Patent Inventor Names
Ya-Yun Cheng
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Chun Hsiung Tsai
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Clement Hsing Jen Wann
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Chih-Hsin Ko
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Patent Jurisdiction
United States Patent and Trademark Office
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Patent Number
11557650
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Patent Primary Examiner
Mouloucoulaye Inoussa
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CPC Code
H01L 23/66
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H01L 27/1203
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H01L 21/76283
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H01L 21/02532
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H01L 21/26533
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H01L 21/76267
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H01L 21/02164
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H01L 21/02236
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H01L 21/02255
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H01L 21/84
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