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US Patent 11600565 Top via stack

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
Date Filed
October 7, 2021
Date of Patent
March 7, 2023
Patent Application Number
17496252
Patent Citations
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US Patent 10622407 Magnetic memory cell and fabrication method thereof
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US Patent 10748901 Interlayer via contacts for monolithic three-dimensional semiconductor integrated circuit devices
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US Patent 10770511 Structures and methods for embedded magnetic random access memory (MRAM) fabrication
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US Patent 10903161 Back end of line metallization structure
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US Patent 10910307 Back end of line metallization structure
‌
US Patent 11195792 Top via stack
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US Patent 11189568 Top via interconnect having a line with a reduced bottom dimension
‌
US Patent 11276637 Barrier-free interconnect structure and manufacturing method thereof
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US Patent 10032643 Method and structure to contact tight pitch conductive layers with guided vias using alternating hardmasks and encapsulating etchstop liner scheme
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US Patent 10243020 Structures and methods for embedded magnetic random access memory (MRAM) fabrication
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
11600565
Patent Primary Examiner
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Laura M Menz
CPC Code
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H01L 23/5226
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H01L 23/528
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H01L 23/53214

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