US Patent 11657199 Method for analyzing electromigration (EM) in integrated circuit
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US Patent 11657199 Method for analyzing electromigration (EM) in integrated circuit
Article
Methods for analyzing electromigration (EM) in an integrated circuit (IC) are provided. A layout of the IC is obtained. A metal segment is selected from the layout according to a current simulation result of the IC. Two first vias are formed over and in contact with the metal segment in the layout. EM rule is kept on the metal segment when a distance between the two first vias is greater than a threshold distance. The EM rule is relaxed on the metal segment when the distance between the two first vias is less than or equal to the threshold distance.
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Is a
Patent Applicant
Current Assignee
Patent Jurisdiction
Patent Number
116571990
Date of Patent
May 23, 2023
0Patent Application Number
178140160
Date Filed
July 21, 2022
0Patent Citations
0
Patent Primary Examiner
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