US Patent 11657205 Construction, modeling, and mapping of multi-output cells

A method includes receiving a design file for a circuit design and receiving a library that defines a cell that includes one or more inputs, a first combinational logic circuit element, a second combinational logic circuit element, a first output, and a second output. The method also includes replacing a plurality of circuit elements in the circuit design with the cell and compiling the circuit design after replacing the plurality of circuit elements with the cell. The first and second outputs of the cell in the compiled circuit design replace a plurality of outputs of the plurality of circuit elements.