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US Patent 11657205 Construction, modeling, and mapping of multi-output cells
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Patent
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Date Filed
September 27, 2021
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Date of Patent
May 23, 2023
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Patent Applicant
Synopsys
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Patent Application Number
17486456
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Patent Citations
US Patent 10346578 Placement-based congestion-aware logic restructuring
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US Patent 8302057 Standard cell library and semiconductor integrated circuit
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US Patent 8607185 Enriching a cell library
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US Patent 10089428 Intelligent cell swapping based on ceiling determination, floor determination, and cell attribute weighting criteria
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US Patent 10691856 System design flow with runtime customizable circuits
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Patent Jurisdiction
United States Patent and Trademark Office
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Patent Number
11657205
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Patent Primary Examiner
Nha T Nguyen
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CPC Code
G06F 2111/20
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G06F 2119/12
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G06F 30/392
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G06F 30/327
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G06F 30/3323
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G06F 30/3315
0
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