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US Patent 11658032 Semiconductor epitaxy bordering isolation structure
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Patent
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Date Filed
March 18, 2021
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Date of Patent
May 23, 2023
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Patent Application Number
17205715
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Patent Citations
US Patent 8729634 FinFET with high mobility and strain channel
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US Patent 8826213 Parasitic capacitance extraction for FinFETs
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US Patent 8853673 Semiconductor device and fabrication method thereof
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US Patent 9337316 Method for FinFET device
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US Patent 10522353 Semiconductor epitaxy bordering isolation structure
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US Patent 10147609 Semiconductor epitaxy bordering isolation structure
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US Patent 10957540 Semiconductor epitaxy bordering isolation structure
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US Patent 7547616 Laser processing method for trench-edge-defect-free solid phase epitaxy in confined geometrics
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US Patent 8487378 Non-uniform channel junction-less transistor
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Patent Jurisdiction
United States Patent and Trademark Office
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Patent Number
11658032
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Patent Primary Examiner
Calvin Lee
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CPC Code
H01L 21/2022
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