US Patent 11670379 Sense line structures in capacitive sense NAND memory

Arrays of memory cells might include a data line, a source, a plurality of pass gates connected in series between the data line and the source, a plurality of unit column structures each having a respective plurality of series-connected non-volatile memory cells connected in series with a respective plurality of series-connected field-effect transistors, wherein a channel of each non-volatile memory cell of its respective plurality of series-connected non-volatile memory cells and a channel of each field-effect transistor of its respective plurality of series-connected field-effect transistors are selectively connected to one another, and a plurality of backside gate lines each connected to the second control gate of a respective pass gate of the plurality of pass gates, wherein, for each unit column structure of the plurality of unit column structures, the channel of a particular field-effect transistor of its respective plurality of field-effect transistors is capacitively coupled to the first channel of a respective pass gate of the plurality of pass gates.