US Patent 11682617 High aspect ratio vias for integrated circuits

An interlayer interconnect for an integrated circuit includes a first line in a first wiring layer, a first via portion integral to and extending from the first line, and a second line in a second wiring layer that is adjacent to the first wiring layer. The interlayer interconnect also includes a third line in the second wiring layer that is a first distance from the second line, wherein the first distance is a pitch of the second wiring layer, and a second via portion integral to and extending from the second line and in electrical contact with the first via portion at an interface to form a via. The via extends a second distance that is at least one-and-a-quarter times the pitch.