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US Patent 11699017 Die yield assessment based on pattern-failure rate simulation
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Patent
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Date Filed
August 23, 2019
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Date of Patent
July 11, 2023
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Patent Application Number
17417223
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Patent Citations
US Patent 9064087 Semiconductor device reliability model and methodologies for use thereof
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US Patent 10539611 Integrated circuit chip reliability qualification using a sample-specific expected fail rate
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US Patent 9639645 Integrated circuit chip reliability using reliability-optimized failure mechanism targeting
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US Patent 11354484 Failure model for predicting failure due to resist layer
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US Patent 7941768 Photolithographic process simulation in integrated circuit design and manufacturing
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US Patent 8856698 Method and apparatus for providing metric relating two or more process parameters to yield
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Patent Jurisdiction
United States Patent and Trademark Office
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Patent Number
11699017
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Patent Primary Examiner
Leigh M. Garbowski
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