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Patent Applicant
Current Assignee
Patent Jurisdiction
Patent Number
Date of Patent
July 18, 2023
0Patent Application Number
173233810
Date Filed
May 18, 2021
0Patent Citations
...
Patent Primary Examiner
The present disclosure relates to micro-via structures for interconnects in advanced wafer level semiconductor packaging. The methods described herein enable the formation of high-quality, low-aspect-ratio micro-via structures with improved uniformity, thus facilitating thin and small-form-factor semiconductor devices having high I/O density with improved bandwidth and power.
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