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US Patent 11710698 Dual-track bitline scheme for 6T SRAM cells
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Patent
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Current Assignee
Advanced Micro Devices
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Date Filed
September 24, 2020
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Date of Patent
July 25, 2023
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Patent Applicant
Advanced Micro Devices
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Patent Application Number
17030821
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Patent Citations
US Patent 9575891 Sidecar SRAM for high granularity in floor plan aspect ratio
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US Patent 8134870 High-density non-volatile read-only memory arrays and related methods
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US Patent 8645893 Method of generating a layout of an integrated circuit comprising both standard cells and at least one memory instance
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US Patent 9251888 SRAM cells with vertical gate-all-round MOSFETs
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US Patent 9275721 Split bit line architecture circuits and methods for memory devices
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US Patent 9898568 Reducing the load on the bitlines of a ROM bitcell array
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Patent Jurisdiction
United States Patent and Trademark Office
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Patent Number
11710698
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Patent Primary Examiner
Dao H Nguyen
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CPC Code
H01L 27/1108
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H01L 27/1116
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H01L 27/0207
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H01L 23/528
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H01L 29/0673
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H01L 29/42392
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H01L 29/78696
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H01L 27/1104
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H01L 23/5226
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