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US Patent 11715695 Size and efficiency of dies

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
0
Current Assignee
Intel
Intel
0
Date Filed
December 17, 2021
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Date of Patent
August 1, 2023
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Patent Applicant
Intel
Intel
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Patent Application Number
17555213
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Patent Citations
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US Patent 9508636 Integrated circuit package substrate
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US Patent 8916981 Epoxy-amine underfill materials for semiconductor packages
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US Patent 8946900 X-line routing for dense multi-chip-package interconnects
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US Patent 9275955 Integrated circuit package with embedded bridge
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US Patent 10615133 Die package with superposer substrate for passive components
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
11715695
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Patent Primary Examiner
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(Vikki) Hoa B Trinh
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CPC Code
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H01L 25/065
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H01L 23/49816
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H01L 25/50
0
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H01L 23/647
0
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H01L 23/5383
0
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H01L 23/5385
0
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H01L 25/0655
0

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