Patent attributes
In certain aspects, a method for operating a memory device is disclosed. The memory device includes memory planes and multiplexers (MUXs). Each MUX includes an output coupled to a respective one of the memory planes, a first input receiving a non-asynchronous multi-plane independent (AMPI) read control signal, and a second input receiving an AMPI read control signal. Whether an instruction is an AMPI read instruction or a non-AMPI read instruction is determined. In response to the instruction being an AMPI read instruction, an AMPI read control signal is generated based on the AMPI read instruction, and a corresponding MUX is controlled to enable outputting the AMPI read control signal from the second input to the corresponding memory plane. In response to the instruction being a non-AMPI read instruction, a non-AMPI read control signal is generated based on the non-AMPI read instruction, and each MUX is controlled to enable outputting the non-AMPI read control signal from the respective first input to the respective memory plane.
