Patent attributes
A memory device includes N memory planes (N is an integer greater than 1), M asynchronous multi-plane independent (AMPI) read units (M is an integer smaller than or equal to N), a first microcontroller unit (MCU), and a multiplexing circuit coupled to the N memory planes, the first MCU, and the M AMPI read units. Each AMPI read unit is configured to provide an AMPI read control signal for a respective memory plane to control an AMPI read operation on the respective memory plane. The first MCU is configured to provide a non-AMPI read control signal for each memory plane to control a non-AMPI read operation on each memory plane. The multiplexing circuit is configured to, in a non-AMPI read operation, direct a non-AMPI read control signal to each memory plane from the first MCU, and in an AMPI read operation, direct each AMPI read control signal of M AMPI read control signals to the respective memory plane from the corresponding AMPI read unit.
