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US Patent 11757609 Serializer/deserializer (SerDes) lanes with lane-by-lane datarate independence

Overview Structured Data Issues Contributors Activity

Is a

Date Filed

May 18, 2021

Date of Patent

September 12, 2023

Patent Application Number

17324025

Patent Citations

US Patent 7961833 Fractional-type phase-locked loop circuit with compensation of phase errors

US Patent 8537956 Techniques for generating fractional periodic signals

US Patent 8866520 Phase-locked loop architecture and clock distribution system

US Patent 8995599 Techniques for generating fractional periodic signals

US Patent 9203418 Phase locked loop circuit

US Patent 9219560 Multi-protocol SerDes PHY apparatus

US Patent 9286825 Apparatus and method for driving LED display

US Patent 9306730 Fractional-N PLL-based CDR with a low-frequency reference

US Patent 9344271 Digital correction of spurious tones caused by a phase detector of a hybrid analog-digital delta-sigma modulator based fractional-N phase locked loop

US Patent 9348358 Clock multiplication and distribution

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Patent Inventor Names

Scott E. Meninger

Patent Jurisdiction

United States Patent and Trademark Office

Patent Number

Patent Primary Examiner

CPC Code

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