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US Patent 11784171 Semiconductor device

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
Date Filed
March 16, 2022
Date of Patent
October 10, 2023
Patent Application Number
17696157
Patent Citations
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US Patent 8816490 Integrated circuit die stacks with rotationally symmetric VIAS
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US Patent 9108841 Microelectronic packages having stacked accelerometer and magnetometer die and methods for the production thereof
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US Patent 9142502 Semiconductor device packaging having pre-encapsulation through via formation using drop-in signal conduits
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US Patent 9177892 Apparatus and method for increasing bandwidths of stacked dies
‌
US Patent 9379063 Semiconductor device and semiconductor chip
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US Patent 9595485 Microelectronic packages having embedded sidewall substrates and methods for the producing thereof
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US Patent 10103124 Semiconductor device
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US Patent 9761565 Microelectronic packages having embedded sidewall substrates and methods for the producing thereof
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US Patent 11329032 Semiconductor device
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US Patent 7098541 Interconnect method for directly connected stacked integrated circuits
•••
Patent Inventor Names
Ae-Nee Jang
Inhyo Hwang
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
11784171
Patent Primary Examiner
‌
Fernando L Toledo
CPC Code
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H01L 21/568
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H01L 21/6835
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H01L 21/78
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H01L 23/3121
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H01L 23/5386
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H01L 23/5389
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H01L 24/19
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H01L 24/20
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H01L 25/50
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H01L 2221/68372
•••

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