US Patent 11805635 Semiconductor memory device

According to one embodiment, a semiconductor memory device includes, on a substrate, a memory region and a peripheral circuit region in which an MOS transistor is formed. The MOS transistor includes a drain region and a source region disposed in a first direction parallel to a surface of the substrate. On a surface of the drain region, a drain electrode is formed to be connected with a contact plug. Further, on a surface of the source region, a source electrode is formed to be connected with a contact plug. When viewed in the first direction, the drain electrode has a region that does not overlap with the source electrode, and the source electrode has a region that does not overlap with the drain electrode.