Patent attributes
A memory device includes a substrate; and a stack structure, including alternately arranged first dielectric layers and electrode layers. In a first lateral direction, the memory device includes an intermediate region and array regions. In a second lateral direction, the stack structure includes a first block and a second block, each including a wall-structure region. In the intermediate region, wall-structure regions of the first block and the second block are separated by a staircase structure. The memory device further includes a beam structure, located in the intermediate region and including at least a plurality of discrete first beam structures, each extending along the second lateral direction and connecting the wall-structure regions of the first block and the second block; and a plurality of second dielectric layers, located in the beam structure. In the first beam structures, the second dielectric layers is alternated with the first dielectric layers.
