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US Patent 11841792 Instructions with multiple memory access modes
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Patent
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Date Filed
December 9, 2019
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Date of Patent
December 12, 2023
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Patent Application Number
16707893
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Patent Citations
US Patent 10970076 Systems and methods for performing instructions specifying ternary tile logic operations
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US Patent 11249766 Coprocessor synchronizing instruction suppression
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US Patent 7590823 Method and system for handling an instruction not supported in a coprocessor formed using configurable logic
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US Patent 7941641 Retargetable instruction decoder for a computer processor
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US Patent 9507593 Instruction for element offset calculation in a multi-dimensional array
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US Patent 10025591 Instruction for element offset calculation in a multi-dimensional array
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US Patent 10338919 Generalized acceleration of matrix multiply accumulate operations
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US Patent 10489479 Matrix multiplication engine
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US Patent 10754649 Computation engine that operates in matrix and vector modes
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Patent Inventor Names
Ron Diamant
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Patent Jurisdiction
United States Patent and Trademark Office
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Patent Number
11841792
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Patent Primary Examiner
Steven G Snyder
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