Patent attributes
An interface circuit, a data transmission circuit and a memory are provided. The interface circuit includes a clock pad, data pads and input buffer circuits, where the clock pad and the data pads are arranged in the first row, and the M data pads are arranged on two sides of the clock pad, half of the M data pads being arranged on each side, where the M input buffer circuits are arranged in the second row and form an axis perpendicular to the first row with the data pads as reference, and the M input buffer circuits are arranged on two sides of the axis, half of the M input buffer circuits being arranged on each side, and where the distance between each input buffer circuit and the axis is smaller than the distance between the data pad corresponding to the input buffer circuit and the axis.
