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US Patent 11842894 Electrical redundancy for bonded structures

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
0
Date Filed
December 21, 2020
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Date of Patent
December 12, 2023
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Patent Application Number
17129632
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Patent Citations
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US Patent 10950547 Stacked IC structure with system level wiring on multiple sides of the IC die
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US Patent 11004757 Bonded structures
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US Patent 11011494 Layer structures for making direct metal-to-metal bonds at low temperatures in microelectronics
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US Patent 11011503 Direct-bonded optoelectronic interconnect for high-density integrated photonics
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US Patent 11031285 Diffusion barrier collar for interconnects
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US Patent 11056348 Bonding surfaces for microelectronics
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US Patent 11176450 Three dimensional circuit implementing machine trained network
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US Patent 11256004 Direct-bonded lamination for improved image clarity in optical devices
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US Patent 11264357 Mixed exposure for large die
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US Patent 11276676 Stacked devices and methods of fabrication
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•••
Patent Citations Received
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US Patent 11967575 Bond enhancement structure in microelectronics for trapping contaminants during direct-bonding processes
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US Patent 12068278 Processed stacked dies
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Patent Inventor Names
Belgacem Haba
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Rajesh Katkar
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
11842894
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Patent Primary Examiner
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Nicholas J Tobergte
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CPC Code
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H01L 25/50
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H01L 24/93
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H01L 24/26
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H01L 25/0657
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H01L 24/06
0

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