US Patent 11853671 Filling vacant areas of an integrated circuit design

Is a

Patent

Patent attributes

Patent Applicant

Pulsic Limited

Current Assignee

Pulsic Limited

Patent Jurisdiction

United States Patent and Trademark Office

Patent Number

118536710

Patent Inventor Names

Graham Balsdon0

Date of Patent

December 26, 2023

Patent Application Number

173422510

Date Filed

June 8, 2021

Patent Citations

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US Patent 7240314 Redundantly tied metal fill for IR-drop and layout density optimization

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US Patent 7340708 Method and apparatus for generating layout pattern

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US Patent 7565638 Density-based layer filler for integrated circuit design

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US Patent 6895567 Method and arrangement for layout of gridless nonManhattan semiconductor integrated circuit designs

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US Patent 6931610 Method for rapid estimation of wire delays and capacitances based on placement of cells

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US Patent 7065729 Approach for routing an integrated circuit

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US Patent 7100135 Method and system to evaluate signal line spacing

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US Patent 7152215 Dummy fill for integrated circuits

Patent Primary Examiner

CPC Code

Patent abstract

Vacant areas of a layer of an integrated circuit design are filled with shapes connected to the appropriate nets.

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US Patent 11853671 Filling vacant areas of an integrated circuit design

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