US Patent 11854974 Advanced node interconnect routing methodology

One aspect of this description relates to an integrated circuit. In some aspects, the integrated circuit includes a first pattern metal layer, a second pattern metal layer disposed over the first pattern metal layer, wherein the second pattern metal layer includes a second plurality of metal tracks extending in a first direction, and a third pattern metal layer disposed between the first pattern metal layer and the second pattern metal layer, the third pattern metal layer including a first metal track segment and a second metal track segment shifted in a second direction from the first metal track segment, wherein the second plurality of metal tracks, and at least a portion of each of the first metal track segment and the second metal track segment are within a double cell height in the second direction.