US Patent 11861287 Integrated circuit development using density-aware border fill

Aspects of the invention include setting a fill mode for a border region of a layer of a macro of an integrated circuit. The border region has a depth defined by a multiple of the size of a tile used to select an area of the integrated circuit for implementation of a design rule check, and the fill mode indicates a fill percentage value or level of fill to be implemented in the border region of the layer of the macro. A fill of the border region of the layer of the macro is performed based on the fill mode. The integrated circuit is finalized and fabricated based on the performing of the fill and passing the design rule check.