US Patent 11876117 Field effect transistor with reduced parasitic capacitance and resistance

A field effect transistor includes a gate structure formed adjacent to a source/drain region, and a spacer structure formed between the gate structure and the source/drain region. The spacer structure includes a top spacer and a bottom spacer, the top spacer includes an airgap having a bottom portion that is wider than a top portion. The wider bottom portion of the airgap is located between the gate structure and the source/drain region.