US Patent 11876523 DPLL timing normalization
Patent 11876523 was granted and assigned to Xilinx Inc on January, 2024 by the United States Patent and Trademark Office.
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US Patent 11876523 DPLL timing normalization
Article
Patent abstract
Embodiments herein describe normalizing an output of a TDC in a DPLL to a resolution of the TDC. A DTC can delay a reference clock which is then input into the TDC. The TDC outputs a digital code indicating a time difference between the delayed reference clock output by the DTC and a clock generated by a DCO in the DPLL. This digital code is normalized to a resolution of the TDC and the result is filtered by a DLF.
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Patent Number
Patent Inventor Names
Ankur Jain0
Hongtao Zhang0
Hsung Jai Im0
Date of Patent
January 16, 2024
0Patent Application Number
180796490
Date Filed
December 12, 2022
0Patent Citations
Patent Primary Examiner
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