Log in
Sign up
Golden has been acquired by ComplyAdvantage.Read about it here ⟶
‌

US Patent 11876523 DPLL timing normalization

Patent 11876523 was granted and assigned to Xilinx Inc on January, 2024 by the United States Patent and Trademark Office.

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
0
Current Assignee
‌
Xilinx Inc
0
Date Filed
December 12, 2022
0
Date of Patent
January 16, 2024
0
Patent Applicant
‌
Xilinx Inc
0
Patent Application Number
18079649
0
Patent Citations
‌
US Patent 11677404 Independently clocking digital loop filter by time-to-digital converter in digital phase-locked loop
0
‌
US Patent 11595048 Faster phase-locked loop locking using successive approximation toward a target frequency
0
‌
US Patent 7888973 Matrix time-to-digital conversion frequency synthesizer
0
‌
US Patent 8508266 Digital phase locked loop circuits with multiple digital feedback loops
0
‌
US Patent 10050634 Quantization noise cancellation for fractional-N phased-locked loop
0
‌
US Patent 10911054 Digital-to-time converter (DTC) assisted all digital phase locked loop (ADPLL) circuit
0
‌
US Patent 11418199 Phase locked loop with parallel phase detection circuits
0
Patent Inventor Names
Hongtao Zhang
0
Hsung Jai Im
0
Ankur Jain
0
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
0
Patent Number
11876523
0
Patent Primary Examiner
‌
Adam D Houston
0
CPC Code
‌
H03L 7/099
0
‌
G04F 10/005
0
‌
H03L 7/093
0
‌
H03L 7/081
0
‌
H03M 1/0854
0

Find more entities like US Patent 11876523 DPLL timing normalization

Use the Golden Query Tool to find similar entities by any field in the Knowledge Graph, including industry, location, and more.
Open Query Tool
Access by API
Golden Query Tool
Golden logo