Patent attributes
The memory device includes a block with a plurality of memory cells arranged in a plurality of data word lines, which are arranged in sub-blocks that are not separated from one another by physical joints or by dummy word lines. A controller is configured to erase the memory cells of a selected sub-block of the plurality of sub-blocks without erasing the memory cells of the unselected sub-blocks. The controller reads data of the edge one word lines of the unselected sub-blocks adjacent the selected sub-block and stores this data in a temporary location external of the block before erasing the memory cells of the selected sub-block. The controller then re-programs the data that is being temporarily stored back into the memory cells of the edge word lines of the unselected sub-blocks after erase of the selected sub-block is completed.
