US Patent 11906579 Wafer-level test method for optoelectronic chips

A method for the testing of optoelectronic chips which are arranged on a wafer and have electrical interfaces in the form of contact pads and optical interfaces which are arranged to be fixed relative thereto in the form of optical deflection elements, e.g., grating couplers, with a specific coupling angle. The wafer is adjusted in three adjustment steps with one of the chips relative to a contacting module such that the electrical interfaces of the chip and contacting module contact one another, and the optical interfaces of the chip and contacting module occupy a maximum position of the optical coupling.