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US Patent 11908890 Isolation structure for stacked vertical transistors
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Patent
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Date Filed
June 14, 2021
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Date of Patent
February 20, 2024
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Patent Application Number
17346806
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Patent Citations
US Patent 9627511 Vertical transistor having uniform bottom spacers
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US Patent 9691850 Vertical transistor with air-gap spacer
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US Patent 9997413 Stacked vertical devices
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US Patent 9831131 Method for forming nanowires including multiple integrated devices with alternate channel materials
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US Patent 10217846 Vertical field effect transistor formation with critical dimension control
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US Patent 9058987 Rare-earth oxide isolated semiconductor fin
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US Patent 9245885 Methods of forming lateral and vertical FinFET devices and the resulting product
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Patent Inventor Names
Kangguo Cheng
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Juntao Li
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Chen Zhang
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Zhenxing Bi
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Patent Jurisdiction
United States Patent and Trademark Office
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Patent Number
11908890
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Patent Primary Examiner
Moazzam Hossain
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CPC Code
H01L 29/78642
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