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US Patent 11916561 Adaptive alignment of sample clocks within analog-to-digital converters

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
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Date Filed
January 24, 2022
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Date of Patent
February 27, 2024
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Patent Application Number
17582641
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Patent Citations
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US Patent 8861667 Clock data recovery circuit with equalizer clock calibration
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US Patent 8902094 Clock generator for use in a time-interleaved ADC and methods for use therewith
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US Patent 9036764 Clock recovery circuit
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US Patent 9608611 Phase interpolator and method of implementing a phase interpolator
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US Patent 9917607 Baseline wander correction gain adaptation
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US Patent 10243614 Method and system for calibrating multi-wire skew
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US Patent 10256845 Symbol timing recovery based on speculative tentative symbol decisions
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US Patent 11545980 Clock and data recovery for multi-phase, multi-level encoding
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US Patent 10903838 Integrated circuit clock management during low power operations
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US Patent 11683023 Programmable delay device enabling large delay in small package
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•••
Patent Inventor Names
Jun Cao
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Boyu Hu
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Delong Cui
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Chang Liu
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Guansheng Li
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Haitao Wang
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
11916561
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Patent Primary Examiner
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Lam T. Mai
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CPC Code
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H03M 1/0624
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H03M 1/0607
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H03M 1/12
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H03M 1/1215
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H03M 1/0836
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