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US Patent 11922223 Flexible data-driven software control of reconfigurable platforms

Patent 11922223 was granted and assigned to Xilinx Inc on March, 2024 by the United States Patent and Trademark Office.

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Is a
Patent
Patent
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Patent attributes

Patent Applicant
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Xilinx Inc
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Current Assignee
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Xilinx Inc
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
119222230
Patent Inventor Names
Kyle Corbett0
Julian M. Kain0
Adam P. Donlin0
Lizhi Hou0
Date of Patent
March 5, 2024
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Patent Application Number
171704270
Date Filed
February 8, 2021
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Patent Citations
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US Patent 7109750 Reconfiguration port for dynamic reconfiguration-controller
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US Patent 6907595 Partial reconfiguration of a programmable logic device using an on-chip processor
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US Patent 7024651 Partial reconfiguration of a programmable gate array using a bus macro
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US Patent 7057413 Large crossbar switch implemented in FPGA
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US Patent 7619442 Versatile bus interface macro for dynamically reconfigurable designs
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US Patent 7640527 Method and apparatus for partial reconfiguration circuit design for a programmable device
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US Patent 7724815 Method and apparatus for a programmably terminated receiver
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US Patent 7746099 Method of and system for implementing a circuit in a device having programmable logic
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...
Patent Primary Examiner
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Daniel D Chang
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CPC Code
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G06F 9/5077
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G06F 9/3836
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G06F 9/3877
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H04L 9/0643
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Patent abstract

Control of a reconfigurable platform can include determining, by a host computer, an interface universally unique identifier (UUID) of an interface of platform circuitry implemented on an accelerator, wherein the accelerator is communicatively linked to the host computer. An electronic request to run a partition design on the accelerator is received by the host computer. In response to the electronic request, the host computer determines an interface UUID for an interface of the partition design and determines compatibility of the partition design with the platform circuitry based on a comparison of the interface UUID of the partition design with the interface UUID of the platform circuitry. The partition design is implemented on the accelerator in response to determining that the partition design is compatible with the platform circuitry.

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