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US Patent 11929337 3D-interconnect

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Is a
Patent
Patent
0

Patent attributes

Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
119293370
Patent Inventor Names
Patrick Variot0
Qwai H. Low0
Chok J. Chia0
Date of Patent
March 12, 2024
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Patent Application Number
173404690
Date Filed
June 7, 2021
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Patent Citations
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US Patent 8035192 Semiconductor device and manufacturing method thereof
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US Patent 8482111 Stackable molded microelectronic packages
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US Patent 8492203 Semiconductor device and method for forming semiconductor package having build-up interconnect structure over semiconductor die with different CTE insulating layers
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US Patent 8557700 Method for manufacturing a chip-size double side connection package
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US Patent 8641913 Fine pitch microcontacts and method for forming thereof
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US Patent 8692135 Wiring board capable of containing functional element and method for manufacturing same
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US Patent 8709933 Interposer having molded low CTE dielectric
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US Patent 8736066 Stacked microelectronic assemby with TSVS formed in stages and carrier above chip
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...
Patent Primary Examiner
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S M Sohel Imtiaz
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CPC Code
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H01L 25/0652
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H01L 24/81
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H01L 21/52
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H01L 23/5386
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H01L 21/568
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H01L 24/17
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H01L 23/5389
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H01L 2224/02331
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...
Patent abstract

A microelectronic assembly comprises a microelectronic element, a redistribution structure, a plurality of backside conductive components and an encapsulant. The redistribution structure may be configured to conductively connect bond pads of the microelectronic element with terminals of the microelectronic assembly. The plurality of back side conductive components may be etched monolithic structures and further comprise a back side routing layer and an interconnection element integrally formed with the back side routing layer and extending in a direction away from the back side routing layer. The back side routing layer of at least one of the plurality of back side conductive components overlies the rear surface of the microelectronic element. An encapsulant may be disposed between each interconnection element. The back side routing layer of the at least one of the plurality of back side conductive components extends along one of the opposed interconnection surfaces.

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