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US Patent 11929425 Nanowire stack GAA device with inner spacer

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
0
Date Filed
June 21, 2021
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Date of Patent
March 12, 2024
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Patent Application Number
17352507
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Patent Citations
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US Patent 9576814 Method of spacer patterning to form a target integrated circuit pattern
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US Patent 9608116 FINFETs with wrap-around silicide and method forming the same
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US Patent 9741811 Integrated circuit devices including source/drain extension regions and methods of forming the same
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US Patent 9786774 Metal gate of gate-all-around transistor
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US Patent 9853101 Strained nanowire CMOS device and method of forming
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US Patent 9881993 Method of forming semiconductor structure with horizontal gate all around structure
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US Patent 9991352 Methods of forming a nano-sheet transistor device with a thicker gate stack and the resulting device
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US Patent 10243061 Nanosheet transistor
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US Patent 10396177 Prevention of extension narrowing in nanosheet field effect transistors
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US Patent 10403739 Method for fabricating semiconductor device
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•••
Patent Inventor Names
Tzu-Chiang Chen
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Tung Ying Lee
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Chao-Ching Cheng
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Tzu-Chung Wang
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
11929425
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Patent Primary Examiner
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Shouxiang Hu
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CPC Code
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B82Y 10/00
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H01L 29/78696
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H01L 29/66795
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H01L 21/02532
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H01L 21/02603
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H01L 21/823431
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H01L 21/823807
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H01L 21/823814
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H01L 21/823864
0
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H01L 21/823878
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•••

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