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US Patent 11948636 Memory device
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Patent
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Date Filed
March 14, 2022
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Date of Patent
April 2, 2024
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Patent Application Number
17693935
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Patent Citations
US Patent 10079059 Memristor cell read margin enhancement
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US Patent 10153429 Memory device
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US Patent 10103324 Memory device and manufacturing method of memory device
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US Patent 10546896 Storage device having variable resistance layer
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US Patent 8456890 Multi-level resistance change memory
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US Patent 8563961 Semiconductor storage device and method for manufacturing same
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Patent Inventor Names
Shigeru Kawanaka
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Yoshiki Kamata
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Yoshiaki Asao
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Misako Morota
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Daisaburo Takashima
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Yukihiro Nomura
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Takahiko Iizuka
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Patent Jurisdiction
United States Patent and Trademark Office
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Patent Number
11948636
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Patent Primary Examiner
Michael T. Tran
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CPC Code
G11C 2213/71
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G11C 2213/75
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G11C 2013/0078
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G11C 5/06
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G11C 13/0069
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