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US Patent 11956127 Incremental topology modification of a network-on-chip

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
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Date Filed
March 3, 2022
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Date of Patent
April 9, 2024
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Patent Application Number
17686364
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Patent Citations
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US Patent 11449655 Synthesis of a network-on-chip (NoC) using performance constraints and objectives
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US Patent 10990724 System and method for incremental topology synthesis of a network-on-chip
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US Patent 11281827 Optimization of parameters for synthesis of a topology using a discriminant function module
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US Patent 6883455 Personal watercraft and buffer member for personal watercraft
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US Patent 6907591 Method and apparatus for performing extraction using a neural network
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US Patent 7096436 Macro design techniques to accommodate chip level wiring and circuit placement across the macro
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US Patent 7398497 Electronic circuit designing method apparatus for designing an electronic circuit, and storage medium for storing an electronic circuit designing method
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US Patent 7587687 System and method for incremental synthesis
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US Patent 7788625 Method and apparatus for precharacterizing systems for use in system level design of integrated circuits
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US Patent 8042087 Method to design network-on-chip (NOC)-based communication systems
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•••
Patent Inventor Names
Moez Cherif
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Benoit de Lescure
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
11956127
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Patent Primary Examiner
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John A Follansbee
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CPC Code
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G06F 15/7825
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G06F 30/392
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G06F 30/394
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H04L 41/145
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