Patent attributes
A memory device includes multiple memory cells configured to store data. The memory device also includes multiple digit lines each configured to carry data to and from a respective memory cell. The memory device further includes multiple sense amplifiers each selectively coupled to respective digit lines and including first and second NMOS transistors and first and second gut nodes coupled to the first and second NMOS transistors, respectively. Each sense amplifier is configured to perform threshold compensation for the first and second NMOS transistors by storing respective voltages at the first and second gut nodes that are proportional to the respective threshold voltages of the first and second NMOS transistors. The sense amplifier also amplifies a differential voltage between the first and second gut nodes by charging the first gut node and discharging the second gut node based at least in part on respective charges of the digit lines.
