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US Patent 11967558 Wafer stacking structure and manufacturing method thereof

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
0
Date Filed
August 9, 2021
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Date of Patent
April 23, 2024
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Patent Application Number
17396776
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Patent Citations
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US Patent 8557680 Semiconductor wafer-to-wafer bonding for dissimilar semiconductor dies and/or wafers
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US Patent 10043769 Semiconductor devices including dummy chips
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US Patent 7056807 Barrier structure against corrosion and contamination in three-dimensional (3-D) wafer-to-wafer vertical stack
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Patent Inventor Names
Jium-Ming Lin
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Shou-Zen Chang
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Chun-Lin Lu
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
11967558
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Patent Primary Examiner
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Errol V Fernandes
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CPC Code
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H01L 23/552
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H01L 21/4857
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H01L 23/5383
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