US Patent 11973122 Nano-FET semiconductor device and method of forming

Embodiments utilize a two layer inner spacer structure during formation of the inner spacers of a nano-FET device. The materials of the first inner spacer layer and second inner spacer layer can be selected to have a mismatch in their coefficients of thermal expansion (CTE). As the structure cools after deposition, the inner spacer layer which has a larger CTE will exhibit compressive stress on the other inner spacer layer, however, because the two layers have a common interface, the layer with the smaller CTE will exhibit a counter acting tensile stress.