US Patent 11973128 Methods for forming multi-gate transistors

A semiconductor device according to the present disclosure includes a channel member including a first connection portion, a second connection portion and a channel portion disposed between the first connection portion and the second connection portion, a first inner spacer feature disposed over and in contact with the first connection portion, a second inner spacer feature disposed under and in contact with the first connection portion, and a gate structure wrapping around the channel portion of the channel member. A shape of a cross-sectional view of the channel member includes a dog-bone shape. By providing the dog-bone shape channel member, a parasitic resistance of the semiconductor device is advantageously reduced, and performance of the semiconductor device may be significantly improved.