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US Patent 11978796 Contact and isolation in monolithically stacked VTFET

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
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Date Filed
December 8, 2021
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Date of Patent
May 7, 2024
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Patent Application Number
17545074
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Patent Citations
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US Patent 9659963 Contact formation to 3D monolithic stacked FinFETs
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US Patent 9773913 Vertical field effect transistor with wrap around metallic bottom contact to improve contact resistance
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US Patent 9997413 Stacked vertical devices
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US Patent 10141448 Vertical FETs with different gate lengths and spacer thicknesses
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US Patent 10192867 Complementary FETs with wrap around contacts and method of forming same
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US Patent 10217674 Three-dimensional monolithic vertical field effect transistor logic gates
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US Patent 10276453 Circuits constructed from stacked field-effect transistors
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US Patent 10297513 Stacked vertical NFET and PFET
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US Patent 10833069 Logic gate designs for 3D monolithic direct stacked VTFET
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US Patent 10381346 Logic gate designs for 3D monolithic direct stacked VTFET
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•••
Patent Inventor Names
Kangguo Cheng
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Ruilong Xie
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Lan Yu
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Chen Zhang
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
11978796
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Patent Primary Examiner
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Mohammad M Hoque
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CPC Code
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H01L 21/823487
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H01L 21/823885
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H01L 27/0688
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H01L 21/823475
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H01L 21/823814
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H01L 29/66666
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H01L 21/823871
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H01L 27/092
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H01L 29/41741
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H01L 27/088
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•••

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