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US Patent 11978799 Method for fabricating transistor with thinned channel

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Patent attributes

Patent Jurisdiction

United States Patent and Trademark Office

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Patent Number

Patent Inventor Names

Amlan Majumdar0

Suman Datta0

Matthew V. Metz0

Jack T. Kavalieros0

Robert S. Chau0

Brian S. Doyle0

Justin K. Brask0

Mark L. Doczy0

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Date of Patent

May 7, 2024

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Patent Application Number

171483300

Date Filed

January 13, 2021

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US Patent 7655989 Triple gate and double gate finFETs with different vertical dimension fins

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Patent Primary Examiner

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CPC Code

0

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Patent abstract

A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.

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