US Patent 12002850 Nanosheet-based semiconductor structure with dielectric pillar

Patent

US Patent 9997519 Dual channel structures with multiple threshold voltages

US Patent 9997598 Three-dimensional semiconductor device and method of fabrication

US Patent 10453850 Three-dimensional semiconductor device including integrated circuit, transistors and transistor components and method of fabrication

US Patent 10510620 Work function metal patterning for N-P space between active nanostructures

US Patent 10516064 Multiple width nanosheet devices

US Patent 10559692 Nanosheet substrate isolation scheme by lattice matched wide bandgap semiconductor

US Patent 10741641 Dielectric isolation and SiGe channel formation for integration in CMOS nanosheet channel devices

US Patent 10593673 Nanosheet with single epitaxial stack forming off-set dual material channels for gate-all-around CMOS

US Patent 10804165 Source and drain isolation for CMOS nanosheet with one block mask

US Patent 9614056 Methods of forming a tri-gate FinFET device

United States Patent and Trademark Office

Dao H Nguyen

H01L 21/823807

H01L 21/823878

H01L 27/092

H01L 29/775

H01L 29/66439

H01L 29/0649

H01L 29/0673

B82Y 10/00

H01L 21/823481