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US Patent 12009351 Plurality of semiconductor devices between stacked substrates
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Patent
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Date Filed
November 12, 2021
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Date of Patent
June 11, 2024
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Patent Application Number
17525833
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Patent Citations
US Patent 7977780 Multi-layer package-on-package system
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US Patent 8198735 Integrated circuit package with molded cavity
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US Patent 8389329 Integrated circuit packaging system with package stacking and method of manufacture thereof
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US Patent 8541872 Integrated circuit package system with package stacking and method of manufacture thereof
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US Patent 9831148 Integrated fan-out package including voltage regulators and methods forming same
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US Patent 10510674 Fan-out package having a main die and a dummy die, and method of forming
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US Patent 10388637 Semiconductor device and method of forming a 3D interposer system-in-package module
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US Patent 10985760 Logic drive based on standard commodity FPGA IC chips using non-volatile memory cells
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US Patent 7687315 Stacked integrated circuit package system and method of manufacture therefor
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US Patent 7749807 Method of fabricating a semiconductor multipackage module including a processor and memory package assemblies
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Patent Inventor Names
Wei-Hao Chang
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Patent Jurisdiction
United States Patent and Trademark Office
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Patent Number
12009351
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Patent Primary Examiner
Alonzo Chambliss
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CPC Code
H01L 23/49822
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H01L 23/49833
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H01L 23/49838
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H01L 23/3107
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H01L 25/165
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H01L 2924/181
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H01L 25/0657
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H01L 21/6836
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H01L 21/78
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H01L 21/56
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