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US Patent 12020949 Subtractive patterning of interconnect structures

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
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Date Filed
September 10, 2021
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Date of Patent
June 25, 2024
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Patent Application Number
17447388
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Patent Citations
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US Patent 9601426 Interconnect structure having subtractive etch feature and damascene feature
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US Patent 9607886 Self aligned conductive lines with relaxed overlay
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US Patent 9761489 Self-aligned interconnects formed using substractive techniques
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US Patent 9773676 Lithography using high selectivity spacers for pitch reduction
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US Patent 9875138 General purpose software parallel task engine
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US Patent 10177031 Subtractive etch interconnects
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US Patent 10157789 Via formation using sidewall image transfer process to define lateral dimension
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US Patent 10685879 Lithographic alignment of a conductive line to a via
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US Patent 8357609 Dual damascene-like subtractive metal etch scheme
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US Patent 8992792 Method of fabricating an ultra low-k dielectric self-aligned via
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Patent Inventor Names
John Christopher Arnold
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Somnath Ghosh
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Dominik Metzler
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Ekmini Anuja De Silva
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
12020949
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Patent Primary Examiner
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Karen Kusumakar
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CPC Code
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G06F 30/3953
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H01L 21/7685
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H01L 21/76885
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H01L 21/32139
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H01L 21/7684
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H01L 21/76897
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