US Patent 12021002 Warpage control of semiconductor die

A semiconductor die includes a semiconductor substrate, a dielectric layer over the semiconductor substrate, a metal structure in the dielectric layer, a first metal pad over the metal structure, a first oxide-based passivation layer over the first metal pad, a second oxide-based passivation layer over the first oxide-based passivation layer, and a bump electrically connected to the first metal pad. The second oxide-based passivation layer has a hardness less than a hardness of the first oxide-based passivation layer.