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US Patent 12021119 Selective liner on backside via and method thereof
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Patent
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Date Filed
July 25, 2023
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Date of Patent
June 25, 2024
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Patent Application Number
18358576
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Patent Citations
US Patent 9372206 Testing of semiconductor chips with microbumps
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US Patent 8772109 Apparatus and method for forming semiconductor contacts
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US Patent 8785285 Semiconductor devices and methods of manufacture thereof
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US Patent 8802504 3D packages and methods for forming the same
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US Patent 8803292 Through-substrate vias and methods for forming the same
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US Patent 8803316 TSV structures and methods for forming the same
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US Patent 8816444 System and methods for converting planar design to FinFET design
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US Patent 8823065 Contact structure of semiconductor device
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US Patent 8860148 Structure and method for FinFET integrated with capacitor
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US Patent 8993380 Structure and method for 3D IC package
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Patent Inventor Names
Li-Zhen Yu
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Chia-Hao Chang
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Lin-Yu Huang
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Kuan-Lun Cheng
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Chih-Hao Wang
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Cheng-Chi Chuang
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Patent Jurisdiction
United States Patent and Trademark Office
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Patent Number
12021119
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Patent Primary Examiner
Jonathan Han
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CPC Code
H01L 29/41766
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H01L 29/66545
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H01L 29/7848
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H01L 2221/1063
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H01L 29/0653
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H01L 29/0673
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H01L 29/4175
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H01L 29/42392
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H01L 29/66439
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H01L 29/665
0
•••
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