US Patent 12022650 Low resistivity DRAM buried word line stack
Patent 12022650 was granted and assigned to Applied Materials on June, 2024 by the United States Patent and Trademark Office.
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US Patent 12022650 Low resistivity DRAM buried word line stack
Article
Patent abstract
Methods for DRAM device with a buried word line are described. The method includes forming a metal cap layer and a molybdenum conductor layer in a feature on a substrate. The method includes depositing the metal cap layer on the substrate by physical vapor deposition (PVD) and depositing the molybdenum conductor layer by atomic layer deposition (ALD) on the metal cap layer.
Infobox
Is a
Patent Applicant
Current Assignee
Patent Jurisdiction
Patent Number
Patent Inventor Names
Annamalai Lakshmanan0
Feihu Wang0
Jacqueline S. Wrench0
Joung Joo Lee0
Seshadri Ganguli0
Srinivas Gandikota0
Yixiong Yang0
Yong Yang0
Date of Patent
June 25, 2024
0Patent Application Number
181492260
Date Filed
January 3, 2023
0Patent Citations
Patent Primary Examiner
CPC Code
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