US Patent 12027416 BEOL etch stop layer without capacitance penalty
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US Patent 12027416 BEOL etch stop layer without capacitance penalty
Article
Patent abstract
An etch stop layer is located on top of a first dielectric layer. A conductive line is located on top of the etch stop layer. A second dielectric layer is located above the first dielectric layer. The second dialect layer is in contact with the first dielectric layer.
Infobox
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Patent Number
Patent Inventor Names
Chanro Park0
Chih-Chao Yang0
Kenneth Chun Kuen Cheng0
Koichi Motoyama0
Date of Patent
July 2, 2024
0Patent Application Number
174765210
Date Filed
September 16, 2021
0Patent Citations
Patent Primary Examiner
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